Article - Backplane Design Commands a Critical Role in New Open Specifications For High Performance Systems

Switched serial interconnects have placed substantial performance demands on backplane design. Open specification organizations VITA (VMEbus International Trade Association) and PICMG (PCI Industrial Computing Manufacturer's Group) are offering new higher speed backplane architectures. Both groups plan to meet their higher speed applications by the use of switched fabric backplane technologies. To meet the challenging design requirements of 3.125 Gbps (Gigabits per second) and 6.250 Gbps signaling and beyond, backplane designers will need to adopt new design methodologies and chose between new materials and PCB fabrication techniques.

The main VITA effort VXS (VITA 41), part of the "VME Renaissance", is a Motorola-led initiative. The VXS design starts with a standard VME64x backplane design and implements a high speed fabric by replacing the existing P0 connector with a new high-speed Multi-Gig 7 Row connector and adding hub slots fully populated with the new connector. The PICMG effort is AdvancedTCA (PICMG 3.0), which is a new form factor and specification led by Intel and Lucent. Advanced TCA stands for Advanced Telecom Computing Architecture (ATCA for short). It is completely new and utilizes the high-speed ZD connector in a new 8U by 280mm form factor, forgoing any backwards compatibility with PICMG's popular CompactPCI. VXS and ATCA both support Ethernet, Infiniband, StarFabric, RapidIO, and PCI Express. Both architectures challenge engineers to find ingenious ways to maintain signal quality at a reasonable cost despite the negative influences higher layer counts, greater signal densities and complex signal interactions. Some believe that the challenges met today at 3.125 and 6.250 Gbps must prepare to solve the same issues as copper signaling moves toward 15 Gbps and possibly beyond.

 

ATCA Backplane

The AdvancedTCA specification allows a variety of architectural implementations. An ingenious channel mapping allows a standard ATCA switch card to support any configuration. For instance, a Dual Star (redundant hub slots running the fabric) implementation could be implemented with cards at either end of the subrack, adjacent in slots one and two or in the middle of the backplane. However, by placing the hub slots in the center of the backplane, the maximum trace length is reduced by half. The result is a big improvement in signal quality because the losses due to dielectric and skin effect will be nearly halved. Further, placing the hub slots in the middle simplifies connections allowing the layer count to be reduced from 18 layers to only 12 layers. This not only saves cost but at 3.2 mm, the thinner board has shorter via stubs. Stubs are one of the most significant loss contributors at gigabit data rates. Figure 1 shows a TDR profile of a stub for a trace situated in the first signal layer. The minimum differential impedance for this layer just below the connector was only 85W and measurements indicated that the differential impedance the signal sees is 102W. This optimized performance (within +/- 2%) is the result of careful trace design, laminate choice and manufacturing control. Tests using passive and active cards with real drivers operating at 3.125 Gbps validated the measurements. The measured eye opening of 509mV leaves plenty of margin as these drivers only require a minimum opening of 200mV. In a live system, performance may be better because the negative effects of the SMA contacts and cables would be eliminated. Measurements and tests both indicate that FR-4 can support speeds of over 5 Gbps with the AdvancedTCA layout. Not all layouts are as generous; the new VXS architecture presented a substantially different challenge -- retaining backward compatible within the existing VME64x backplane layout constraints.

VXS Backplane

For VXS, the new Multigig RT P0 connector and hub slots carry the high-speed switch fabrics while the P1 and P2 connectors will support legacy VME64x cards. This design maintains full backward compatibility while adding high-speed serial fabric connectivity. VITA 41 designers will have the flexibility of using the P2 connector in a payload slot for the parallel VME64x legacy cards or the P0 connector in the same payload slot for an Infiniband or Rapid IO fabric connection. In the future StarFabric and PCI Express may also be supported.

The existing 2mm HM P0 connector would not support speeds over 1 Gbps well; the new VXS design uses a 7-row MultiGig RT connector to handle speeds of up to 10 Gbps. However, accomplishing the dense routing on a .8-inch pitch with signals at 3.125 Gbps or higher requires some creativity. Even a mid-sized 12-slot Dual Star VXS backplane configuration forces the designer to make some difficult choices.

In this example the 12-slot Dual Star VXS backplane requires as many as 18 layers. Avoiding undesirable stubs for upper layer backplane traces presents two possible options One choice would be to have these worse case vias back-drilled a costly fabrication process which removes the unused portion of the plated via structure below the layer at which the signal is terminated. The other choice is to minimize the length of via stubs by choosing a laminate with a lower dielectric constant. This will allows the 100-ohm differential impedance to be achieved with thinner PCB layers. A lower dielectric constant (Er) is not the only characteristic that makes higher performance board materials attractive. Materials such as Nelco 4000-13SI, Rogers 4350 and Mashusutta's Megtron 5 also have significantly lower loss tangent values at these higher frequencies (Nelco 6000-13SI is not presently available). The loss tangent value indicates a materials degree of undesirable interaction with a signal at a given frequency.

PCB choices can be difficult to measure and because a close relationship between laminate supplier and board fabricator is essential to achieve consistently high yield rates as well as acceptable long-term reliability (MBTF). Listen to your supplier. There are many good materials but the best choice will be the one that your vendor has already optimized from a processing perspective.

As has been done for AdvancedTCA, placing the hubs centrally for a VXS layout in most Dual Star configurations is a good choice. Because of the superior loss tangent characteristics, lower Er and other performance considerations, Bustronic chose a low loss laminate for its 12-slot dual star VXS prototype. For other future configurations that are less challenging (smaller slot counts, Single Star configurations, etc.) a standard FR-4 laminate may be sufficient.

Conclusion

To summarize the design challenges, in general terms, there are three basic constraints that will determine how the design engineer may achieve an interconnect design goal at these higher speeds. These constraints are, how long a backplane path, the desired data rate and how many signals must be packed per inch of PCB edge. The requirements for these three constraints will drive the choice of semiconductor technology, PCB materials, connectors, via construction, and even other more exotic constructions. Aside from the VITA and PICMG groups that are today implementing specific backplane architectures at 3.125 and 6.250 Gbps, there are study groups within the IEEE and the Optical Internetworking Forum (OIF) that are addressing design issues for single channel backplane interconnects capable of up to 10 Gbps data rates (see sidebar). Regardless of the approach taken, the higher data rates in ATCA, VXS, and other designs require creative backplane design solutions.

Michael Munroe
Technical Product Specialist
Bustronic

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