VPX and the Brave New World of Flexible Hybrid Backplanes

Michael Munroe, Elma Bustronic

The VPX backplane architecture represents a major leap forward for system integration flexibility through its support of flexible hybrid configurations. These configurations include flexible topologies, multiple signaling protocols, and hybrid core architectures (i.e., mixed VPX and legacy VME64x configurations) and multiple power choices. Earlier backplane specifications, such as VME, strictly defined slot usage. These previous backplane architectures defined how connector pins would be used by a given board, and how each card slot would be connected to the next card slot. These backplanes limited the system capability, because key architectural features were defined rigidly from the start. For example, decisions about system connectivity; (how boards are connected to each other) determined a specific interconnect topology. VPX was designed to enable end-users to employ any single or combination of the popular interconnect topologies in a single backplane to best fit any given application.

The VPX Core standard provides for the development of hybrid backplanes. The VPX architecture is designed to simultaneously support a mix of bus segment. For example, these integrated bus segments can be configured in full mesh, pipeline or single or dual star topologies. It is also permissible to have some slots configured as legacy parallel VME. Of the seven connectors in each slot, numbered 0-6, connectors J1 to J6 may be implemented for either differential signals or single ended signals. The VPX architecture offers maximum system flexibility unlike conventional architectures with defined signaling and interconnect topologies. This flexibility allows a user to use exactly as many pins and connection configurations, etc, as are needed for the specific application. VPX defines a standard card layout and standard mechanics but lets system engineers connect-the-dots between them so as to conform to the exact needs of their application .

The term, “hybrid backplane” typically suggests one of two meanings, either bringing together heterogeneous backplane architectures (legacy hybrid) such as fabric-based VPX and parallel VME64x, or the mixing and matching of different types of network topologies (hybrid topologies), such as mesh and stars. There are, in fact four different types of hybrid backplanes. In addition to the hybrid types just mentioned, VPX adds the support of hybrid protocols (mixing different fabrics, for example SRIO and Infiniband – on different channels or bus segments) and a hybrid power approach that allows the integrator to chose the primary voltage for his application from the choices: 3.3VDC, 5VDC, 12VDC, or 48VDC power. Thus, the VITA 46 (VPX) backplane architecture uniquely embraces all four of these hybrid concepts into a single flexible backplane standard.

Legacy Hybrid

The idea of Legacy Hybrid has been a familiar one in VME development over the years. For example, in a VXS backplane it is possible to combine side by side, legacy VME64x boards with the 2mmP0 connector alongside fabric-based boards with the differential Multi-Gig J0 connector. In the legacy VME64x slots, boards such as a Curtiss-Wright SBC running StarFabric over the 2mm HM P0 connector while other systems could populate the legacy VME64x slots with cards based on Ethernet or Myrinet serial protocols. Either of these legacy choices could be combined with multiple slots of newer VPX fabric cards based on Serial RapidIO such as the Curtis Wright CHAMP AV6. For VPX users, the Legacy Hybrid approach is a transitional, bridging approach that makes it easier for people to use the available VPX boards immediately by combining them with other existing legacy boards. Some early adopters have expressed an interest for hybrid backplanes with large numbers of legacy slots and smaller numbers of VPX slots, For example one proposed backplane offers 9 slots of legacy VME and 3 slots of VPX. (See diagram x for an example). As more VPX boards become available, it’s expected that the ratio will switch toward more VPX slots and fewer VME.

To implement Legacy Hybrid support, a VPX standard which mapped signal locations for parallel address and other system signals required by older VME boards onto one or more VPX slots. These special VPX slots are for cards that are capable of communicating across both a serial VPX protocol as well as the parallel legacy VME protocol. Again it can noted that not all VPX slots in such a Legacy Hybrid backplane would be required to support dual architecture cards. Part of the challenge in developing a Legacy Hybrid VPX/VME backplane involves proper wiring that ensure that electrical signals are assigned to the VPX slot in a way that meets the constraints of signal routing while maintaining signal integrity by keeping sensitive signals away from each other.

Hybrid Topologies

Hybrid topologies represent a second type of flexibility which can be provided by a hybrid VPX backplane. Many of the leading vendors of embedded computer boards who collaborated within the VITA 46 Working Group had different fabric interconnect topologies in mind for their markets. Some applications are best served by pipeline architectures, other types of applications are ideal for mesh topologies. It is not unusual, however, in an ideal system to combine topologies so one group of cards are connected in a mesh and other groups of cards pass data from one card to another in a straight pipeline. For this reason it was agreed from the very beginning that the VPX backplane would allow system architects to select the ideal mix of topologies. The result is a VPX standard that enables system designers to select a single fabric and topology to address a very specific problem or instead use multiple fabrics and topologies as their application may require.

To define the proper usage of a variety of optional topologies and their mixed use, the VITA 46 working group developed specific “dot-specs” that define each supported topology. VITA 46.0 is the base specification and sets the requirements for the backplane’s differential signal assignments and location of channels. It also defines where the (+) and (-) differential pair pins are located, and for differential pairs, and the location of single-ended signals which are interspersed.

VITA 46.1 defines parallel VME within a VPX slot as was discussed earlier. The VITA 46.1 dot-spec allows the integrator to specify how many slots will support the parallel VME signals. All slots would also conform to the basic requirements of VITA 46.0.

VITA 46.9 defines I/O pin usage for PMC/XMC cards. PMC and XMC sockets enable users to add additional functionality to a base card. This functionality can be graphics processing signal or data conditioning or a special protocol interface. While some XMC sockets will not require any backplane I/O many applications utilizing XMC sockets will use the backplane as an I/O port. It is for this purpose that VITA 46.9 defines the signal assignments for various configurations. For instance a 6U card may have one or two XMC sockets requiring backplane IO. Another configuration might be one or two PMC sockets. An example of a product that provides increased backplane I/O via two 46.9-compliant PMC/XMC sites is Curtiss-Wright’s VPX6-185 8641-based single board computer.

VITA 46.10 defines the use of rear-transition modules on VPX. This is driven by I/O intensive applications such as an interface to demanding applications such as medical X-Ray processing, storage area networks, and antenna arrays.

There are several system functions that in some cases would benefit from having a switched serial fabric for utility functions such as system control, application configuration access or other basic communication needs. To standardize the implementation of a single or dual star control channel VITA 46.20 is being defined. By standardizing the channel maping of such a utility channel, it will allow vendors to offer switch cards to provide this access. One of the popular implementations of this newly proposed standard will be 3U and 6U unmanaged x2 Gigabit Ethernet fabric switches.

The VITA 46 dot-specs also enable users to define special electrical requirements for a specific fabric protocol. The dot specifications are also where the granularity and flexibility of data channels. For instance, a dot specification can define support for x2, x4, x8 duplex channels and so forth. Limiting support to a smaller set of channel widths would reduce cost. Supporting a wide number of channel widths will increase flexibility.

Because some topologies and channel width may be ideal for one aspect of an application and another topology may be ideal for a different application task, system integrators may wish to define multiple bus segments in order to support groups of boards with different connectivity requirements in a single system. Although these different topologies can be segregated into separate slots, it is also possible that two different topologies can overlay each other within a common board set by assigning specific connector segments to different interconnect topologies. For example one backplane segment may be designated for a slot to slot pipeline topology while another segment supports a distributed mesh for a cell architecture. A single slot might be configured with the specific IO ports needed for an SBC serving as the system consol and other slots might be provided with maximum IO to multiple XMC sockets.

Channel Granularity

The user may opt to overlay the entire backplane with a distributed Ethernet star. A 6U VPX slot, which can be viewed as 192 differential pairs, can be divided into 24 duplex x4 channels, or into 48 full duplex x2 channels, or a combination of x2 and x4 channels. Such channel definitions are frequently referred to thin pipes and fat pipes. Thin pipes could be used for control functions and fat pipes used by application for data transport. With regards to fabric channel mapping, the standard core fabric provisioning for a VPX payload slot is 4 ports of x4 duplex channels.

While the VPX backplane is essentially fabric agnostic, with only link fabric mapping driving backplane design time, there are some other choices to be determined by the various subsidiary documents that will drive the cost to implement any a card for any given subsidiary specifications. Subsidiary documents must define the support of channel aggregation and granularity. For instance, the Ethernet subsidiary specification may not choose to support every possible protocols (i.e. 1000 BASE-T, 1000BASE-KX, 1000BASE-KX4, 10GBASE-KR). The Infiniband PCI Express and Serial Rapid IO dot specifications may each support their own assortment of possible link granularity (i.e. x1 through x16) and while these considerations may not always require different backplanes designs, they will certainly determine the implementation cost and flexibility of cards for each subsidiary protocol that is defined. The requirements that determine how many links will be aggregated to make a channel and the minimum or maximum number of links that form a channel are spelled out in VITA 46.3, for SRIO, VITA 46.4 for PCIe, and VITA 46.8 for Infiniband.

Flexible Protocols

The concept of flexible protocols goes back to the earliest usage of serial fabrics when users realized that a serial channel is essentially fabric agnostic and could be used for any number of serial protocols. Mixing protocols on a VPX backplane is relatively simple from the electrical requirement perspective, which makes it easy for the backplane manufacturer to address. This is because a differential pair that is good at handling SRIO, is also ideal for Gigabit Ethernet, PCE, Infiniband, or a SERDES direct protocol (such as Aurora).

VPX is flexible enough to support the wide variety of fabrics and the different topologies that they prefer. For example, Ethernet, PCI Express, and Infiniband are typically configured in a centralized topology like Star or Dual Star, while SRIO and the FPGA protocols Aurora (Xilinx) and Serial Lite (Altera) are frequently configured in mesh environments.

The signaling requirements for different protocols are really electrically identical or nearly identical. VPX provides the bandwidth to support the full range of high-speed protocols. While VME could support 10/100 Mbit Ethernet, and with the 2mm connector strived to support 1 GigE, it wasn’t until the high performance MultiGig connector emerged (which VPX uses) , that supports data rates in excess of 5Gb/s, reaching as high as 10 Gb/s, became practical and achievable.

Flexible protocol backplanes are important because for many applications already require two protocols. For example, in an FPGA-based system using a board such as Curtiss-Wright’s CHAMP-FX2 VPX FPGA processor board, you probably need to have one protocol for passing data between boards in a point-to-point architecture, but you may also need to have an Ethernet channel via which you can initiate processes or reprogram boards, which sometimes may be done through the front panel, but a standalone system without an operator present may require a communication card to talk to any one of the cards, which could be done via a Star architecture like that defined by VITA 46.20.

Power Flexibility

One type of backplane hybrid that is generally less familiar than those considered above is the Power Flexibility. In a system there may be a mix of cards that have different power requirements, for example there may be Telco cards that use 48V and other cards that use a vehicular supply of 24V. While the topology hybrid design demands the user to consider how the application will use the cards and what the data requirements will be, the power problem is simpler, in that challenge is identifying how much power each board requires. But for the backplane vendor routing and labeling power connections can be just as complex for as the challenge of building a topology hybrid or legacy hybrid backplane.

Conclusion

VPX cards are now starting to emerge from vendors such as Curtiss-Wright, Micro Memory, GE Fanuc/Radstone and Mercury. While in the past, standard backplanes were available before the before the cards were developed, today because of all the flexibility that VPX brings in terms of protocols and topologies, backplane vendors are waiting to see what board connectivity board vendors are going to offer and some board vendors are waiting to see what preferences are going to be popular with customers. Regardless of the final system requirements, it is likely that laboratory development will take place on standard configurations such as the 5 slot mesh backplane example found in chapter 7 of the VITA 46.0 document.

One unique approach being proposed by Elma Bustronic Corp, is for a custom VPX development backplane, utilizing SATA2 (tm) cables to interconnect multiple channels between slots. This approach will the user to reconfigure slot to slot connections with the backplane itself providing mechanical alignment, system signals and power distribution. The final system connections would be fully implemented within a backplane for superior signal integrity and greater reliability.

When designing a hybrid VPX backplane, customers should ask themselves the following questions, 1) How many slots 2) What subsidiary protocol will each slot support? (i. e. 46.1, 46.2, 46.3, 46.4, 46.20 etc.) 3) What interconnections topology will be required from slot to slot (i.e. meshes, rings, stars or some combination),4) What voltages will be supported at which slots? 5) Which slot(s), if any, will need rear transition modules?

For the rugged, ESD-protected complement standard to VPX, VPX-REDI (VITA 48) the key question will be cooling. VITA 48 supports forced air convection cooling (48.1); conduction cooling (48.2); and liquid flow through modules 48.3 for inboard quick disconnects and 48.4 with outboard quick disconnects. ATCA defines a maximum of 200 watts per slot, MicroTCA defines a maximum of 60 watts per slot, legacy VME provided approximately 120 watts per slot, and VME64x provided up to 174 watts per slot. With Vs1 and Vs2 committed to 48VDC VPX could theoretically provide up to 2,222 watts per slot. (including the 5VDC power on Vs3) However, before you start figuring how you might fit triple stack FPGAs edge to edge on a single 6U-160 card, remember that the most advanced flow through cooling techniques are not expected to cool cards consuming over 500 watts per slot.

(Sidebar: matching topologies with protocols?)

VITA 46.0 Base Specification
VITA 46.1 Parallel VMEbus
VITA 46.2 Parallel PCI
VITA 46.3 Serial RapidIO™
VITA 46.4 PCI Express
VITA 46.5 Hypertransport
VITA 46.6 Gigabit Ethernet
VITA 46.7 10Gbit Ethernet
VITA 46.8 InfiniBand
VITA 46.9 XMC and PMC I/O mapping
VITA 46.10 Rear Transition Modules RTM
VITA 46.20 GigE Control Plane

Top