Measuring the Actual Performance Characteristics of AdvancedTCA Backplanes with Signal Integrity Analysis When a high-speed product specification is relatively new, there is often little information on the actual performance characteristics of the products as opposed to the theoretical performance given as it is being developed. Perhaps there were simulation studies that provided a basis for the hypothesized performance, as was done for AdvancedTCA. But different companies have different design practices and capabilities. How do you know if a specific vendor is providing a product that performs adequately? Particularly with the high-speeds of the signals, how do we know if the signal integrity truly holds up across the backplane design? This article will show how the true performance characteristics of an AdvancedTCA backplane can be studied through Signal Integrity engineering, along with several examples of the measurements. Signal Integrity Engineering Faster PCB designs are by nature more sophisticated and delicate. At higher clock speeds, the PCB demands cleaner signal transmission without compromising the stability of the system. This is where Signal Integrity engineering comes into play. Simply put, signal integrity studies the design of high-speed circuits that can accommodate cleaner signals passing through them. Cleaner signals, in turn, enable engineers to identify and minimize sources of distortion in data transmission, which could otherwise disrupt timing of the digital logic. Signal integrity issues such as reflections, cross talk, frequency dependent transmission line loss and dispersion can significantly lead to poorer system performance propagating through the interconnect. These SI issues arise from via, power/ground coupling, RLC effects in signal lines, etc. With 3.125 Gbps to 6.250 Gbps signal speeds across the backplane and beyond, an AdvancedTCA backplane is very susceptible to these types of issues. To ensure customers the optimum performance, backplane simulation/characterization studies can be performed. In this article, we will focus on the characterization of Bustronic's 5-slot Mesh AdvancedTCA backplane. In future articles and white papers, we will discuss simulating the expected results of a backplane before it gets designed. The 5-slot ATCA backplane was a 3X Mesh in a 18 layer controlled impedance edge-coupled stripline design. We worked with NESA and Teraspeed on the development of a new ATCA backplane Signal Integrity (SI) test card. The test card is used to accurately measure the impedance, transmission, channel skew, eye-diagram and channel crosstalk characteristics of an ATCA backplane. This SI test card was designed specifically to meet the testing requirements set forth in the PICMG 3.0, ATCA Specification. AdvancedTCA calls out specific requirements for several parameters of signal integrity. ATCA Backplane Signal Integrity Requirements (Base and Fabric Interface requirements) 1. The differential impedance of the backplane and probe board serial
links for Base and Fabric interfaces should be 100 Ohm +- 10% The studies below will show the backplanes performance relative to the specification's requirements. Fabric Impedance The first measurement we will discuss on the 5-slot ATCA backplane is the fabric impedance. The characteristic impedance of the transmission line is defined by the ratio of the voltage and current at any point as a test pulse travels down a pair of differential backplane traces. [1]. Impedance mismatches (due to vias and connectors) and variations can cause reflections, which degrade the signal quality. Time Domain Reflectometry (TDR) produces a positive-going incident wave that is applied to the device under test (DUT). The step-pulse travels down the DUT at the velocity of propagation of the line. If the load impedance is equal to the characteristic impedance of the line, no wave is reflected and all that will be seen on the oscilloscope is the incident voltage step recorded as the wave passes the point on the line monitored by the oscilloscope. At every impedance discontinuity that the signal encounters, part of the incident wave is reflected. The reflected voltage wave will appear on the oscilloscope [2]. The resulting waveform is like a road map of the impedance variations across the trace. The worst case connection paths were tested only. That means the longest net length traces were tested. The differential impedance of the backplane and board serial links for Base and Fabric interfaces should be 100 Ohm+- 10%. The measured average value of differential trace line is 107 ohm. Even the worst-case scenario performed within the required range. For our measurements, we used a wide-bandwidth oscilloscope with 18 GHz measuring bandwidth, high-quality cables, termination resistors, and IConnect analysis software from TDA systems. Fig1:
There are six synchronization clock buses in the architecture. The six buses are divided into 3 groups of two differential pairs each. Each clock bus is implemented as a differential pair that connects to all Slots through pins in the Zone 2 connectors. The buses are fully symmetric so that receivers and transmitters (i.e., bus drivers) can be located in any slot. The first pair of clock buses (CLK1A and CLK1B) is dedicated to redundant 8 kHz system clock signals. This frequency is the fundamental frequency used for all digital telephony transmission systems. The CLK1A+- is tested . CLK1A+- net is tested. The differential impedance of the backplane serial links for the clock interfaces on the Backplane should be 130 Ohm +- 10% .The measured average value of clock trace line is 124 ohm. Again, the results were well within the limits. S-Parameter Scattering parameters can capture the reflection and transmission from junctions in backplanes. The ratio of the reflected power to the incident power is the return loss and the ratio of the transmitted power to the incident power is the Insertion loss. These values are derived for defined incremental frequency steps over a range of frequencies that covers the design requirements for the backplane. For AdvancedTCA this was the range from 0 to 5 GHz. Insertion L Fig2a.: S21 Test Set up Fig2b: S11 Test Set up
The results show that both the Insertion and Return Loss on the 5-slot ATCA backplane under test do not violate the Insertion loss and Return limits for PICMG 3.0.
WaveformFig3:Layer11_Sig05_AB8_S1Waveform Crosstalk Crosstalk refers to undesired signals induced on traces or paths due to other nearby signal. Near-end (backward/reversed) crosstalk is defined as the crosstalk seen on the victim line at the end closest to the driver (aggressor). Far-end (forward) crosstalk refers to the crosstalk observed on the victim line farthest away from the aggressor [1]. To achieve accurate results, we used high-quality cables, termination resistors, and adapters with our PCB under test. Below is the result for Far End Crosstalk.
Fig4: Layer11_Sig05_FEXT Waveform
From the FEXT graph, The aggressor amplitude is 200 mV, and the crosstalk in connector area and backplane trace area are in Microvolt range (which is negligible) From our Next measurement, the aggressor amplitude is 200 mV, and the crosstalk in the connector area is 4mV(only 2%). Eye Diagram An eye diagram takes the results of a simulation driven by a long, multi-cycle bi sequence, superimposes each bit period over the top of all others-like a time exposure photograph-and presents waveforms that have open areas shaped something like a human eye. The larger the eye opening, the better the results. The most common type of stimulus used in eye-diagram generation is the "PRBS" or "pseudo-random bit sequence." [3] From the result, we can see, trace on layer nine which is routed on slot1 to slot5 still has a more than adequate eye opening (86%) at a PRBS 2^10-1 of 3.125Gbps. 3.125Gbps
Reference Slot1 to Slot 5 Eye Height: 500mV Eye Height: 430mV
Performance Assured As you can see from the results above, we were able to show that the 5-slot ATCA backplane performance was well within the specified requirements, even taking the worst-case scenarios. Simulation and characterization capabilities will be increasingly important as we continue to move to higher-speed switch fabric technologies. Bustronic will continue to publish various SI studies in the coming months. This includes a study on pre-design simulation of an AdvancedTCA backplane. If you have any questions or would like further information of SI capabilities and studies, visit www.bustronic.com or contact us at 510-490-7388. Mahamud Khandokar Reference: [1] Stephen H. Hall, Garrett W. Hall, James A. McCall, "High-Speed Digital System Design". [2] "Time Domain Reflectometry Theory" Agilent Application Note 1304-2. [3]"3.125 Gbps with your Hair on Fire Simulation-Based Signal-Integrity Analysis of Digital Interconnects at Multi-Gigabit Speeds" by Bill Hargin , High-Speed Systems Design , Mentor Graphics Corporation. |
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